As is well known, forming an isolation region between two zones of an integrated circuit establishes electrical separation therebetween, and is usually achieved by the interposition of an isolation structure.
One possible isolation structure of a known type is depicted in FIG. 1a, and is described in Patent Application EP 91830151.6, filed on Apr. 17, 1991 by the applicant, and in U.S. Pat. No. 5,432,376, which issued on Jul. 11, 1995 and is based on the EP application.
For simplicity, FIG. 1a shows a circuit including a single low-voltage driver transistor of the npn type and single power transistor, also of the npn type.
This known structure, as described in detail in the above-mentioned patent, uses a diffused zone 4 of the n type, called the junction isolation zone, which separates regions 30 and 31 of the p type to isolate the power stage from the driver circuit.
While being advantageous from several aspects, this solution has a drawback in that it is limiting of the breakdown voltage for the resultant components due to inherent features of the method used, which provides for different concentrations of the various dopants.
Also directed to isolate the power stage from the driver circuit is a second solution, illustrated in FIG. 1b, wherein a dielectric isolation region 14' is provided instead of the diffused region 4.
While achieving its objective, not even this second solution is devoid of drawbacks.
Most serious of such drawbacks is one inherent to the processing sequence used, on account of the isolation region being defined directly after growing the last epitaxial layer, and in any case before forming either the power or the control components. Due to the materials used to form the dielectric isolation region 14' having different expansion coefficients, during the high-temperature, typically above 800.degree. C., thermal cycles required to form the active regions of the components, the monocrystalline silicon lattice is subjected to considerable stresses which may later be relieved in an unelastic manner by dislocations and other crystal defects likely to impair the circuit performance and functionality.
In general, a temperature below 700 degrees Celsius is often considered a low temperature, and a temperature above 800 degrees Celsius is often considered a high temperature.
This allows some processing steps which entail deposition of materials to be classified as low-temperature steps, whereas the oxidation and diffusion steps would be steps carried out at high temperatures.
However, this is but one example of an isolation scheme known as Deep Trench Isolation (DTI). Comprehensive reviews of known technological approaches are to be found in the references listed here below:
[1] H. Goto and K. Inayoshi, "Trench Isolation Schemes for Bipolar Devices: Benefits and Limiting Aspects," Proceedings of the 17th ESSDERC (Bologna, September 1987), 369-372; PA0 [2] C. Rapisarda, R. Zambrano, F. Baroetto and P. J. Ward, "Reliable Deep Trench Isolation Scheme for High Density, High Performance Bipolar Applications," Isolation and Trench Technology Symposium (Seattle, October 1990), Proceedings of the 178th Electromechanical Society Meeting, 412-413; and PA0 [3] F. Y. Robb et al., "High Voltage Deep Trench Isolation Process Options," Isolation and Trench Technology Symposium (Seattle, October 1990), Proceedings of the 178th Electromechanical Society Meeting, 408-409.
References [1] and [2] above deal with the application of the technique to high-performance bipolar devices.
To provide effective isolation, the trench should be extended through the n-type epitaxial layer, approximately 1 micron thick.
The depth attained by the isolation, with this approach, does not exceed 5 microns.
Also known is that, to achieve good planarization, the trench width should not exceed 2 microns, for otherwise, very thick layers of polycrystalline silicon, or polySi, would have to be deposited, resulting in decreased productivity and increased cost of the process.
Some problems connected with the extension of this technique to devices which are to operate at higher voltages are discussed in Reference [3] above.
It is emphasized there, for example, that the trench depth should be increased, because the epitaxial layers to be etched are thicker, being on the order of 15 to 25 microns thick; on the other hand, trenches with aspect ratii (ratio of trench depth to width) higher than 10 are difficult to make.